The present invention relates to a technique for manufacturing semiconductor devices, and more particularly, a technique suitable for use in manufacture of a semiconductor device which includes wirings coupled to electrode pads of a semiconductor chip.
The background art of a wafer process package (WPP) or a wafer level package (WLP), which belongs to the technical field of the present invention, is disclosed in, for example, Japanese Unexamined Patent Application Publications No. 2009-246218, No. 2008-021936, and No. 2007-157879.
Japanese Unexamined Patent Application Publication No. 2009-246218 (Patent Document 1) describes a semiconductor device and a manufacturing method thereof, in which pads are provided over a semiconductor chip, each pad having a probe region and a coupling region. In the semiconductor device, a probe mark exists at the pad in the probe region positioned on the outer peripheral side of the semiconductor chip with respect to the coupling region, and a rewiring is formed to extend from the coupling region toward the center side of the semiconductor chip.
Japanese Unexamined Patent Application Publication No. 2008-021936 (Patent Document 2) describes another semiconductor device and manufacturing method thereof. The semiconductor device is comprised of a rewiring layer including a wiring pattern having a linear portion and a post electrode mounting portion, a post electrode provided over the post electrode mounting portion, and an external terminal mounted over a top surface of the post electrode. The post electrode has its button surface with an outline intersecting at least two points of an outline of an upper surface of the post electrode mounting portion.
Japanese Unexamined Patent Application Publication No. 2007-157879 (Patent Document 3) describes a further semiconductor device and manufacturing method thereof, in which a plating underlayer is formed by electroless plating to be coupled to a terminal electrode, and at least a part of a rewiring layer coupled to the plating underlayer over the terminal electrode is formed of a plated layer.